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INTEGRATED CIRCUITS
SCN2652/SCN68652 Multi-protocol communications controller (MPCC)
Product specification IC19 Data Handbook 1995 May 01
Philips Semiconductors
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
DESCRIPTION
The SCN2652/68652 Multi-Protocol Communications Controller (MPCC) is a monolithic n-channel MOS LSI circuit that formats, transmits and receives synchronous serial data while supporting bit-oriented or byte control protocols. The chip is TTL compatible, operates from a single +5V supply, and can interface to a processor with an 8 or 16-bit bidirectional data bus.
FEATURES
* DC to 2Mbps data rate * Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC * Byte-control protocols (BCP): DDCMP, BISYNC (external CRC) * Programmable operation
- 8 or 16-bit tri-state data bus - Error control - CRC or VRC or none - Character length - 1 to 8 bits for BOP or 5 to 8 bits for BCP - SYNC or secondary station address comparison for BCP-BOP - Idle transmission of SYNC/FLAG or MARK for BCP-BOP
APPLICATIONS
* Intelligent terminals * Line controllers * Network processors * Front end communications * Remote data concentrators * Communication test equipment * Computer to computer links
* Automatic detection and generation of special BOP control
sequences, i.e., FLAG, ABORT, GA
* Zero insertion and deletion for BOP * Short character detection for last BOP data character * SYNC generation, detection, and stripping for BCP * Maintenance mode for self-testing * TTL compatible * Single +5V supply
PIN CONFIGURATION
INDEX CORNER CE RxC RxSI S/F RxA RxDA RxSA RxE 1 2 3 4 5 6 7 8 40 MM 39 TxC 38 TxSQ 37 TxE 36 TxU 35 TxBE 17 34 TxA 33 RESET 32 VCC DIP 31 DB00 30 DB01 29 DB02 28 DB03 27 DB04 26 DB05 25 DB06 24 DB07 23 DBEN 22 BYTE 21 A0 TOP VIEW NOTE: DB00 is least significant bit, highest number (that is, DB15, A2) is most significant bit. 18 TOP VIEW Pin Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC CE RxC RxSI S/F RxA RxDA RxSA RxE GND DB08 NC DB09 DB10 DB11 DB12 DB13 DB14 DB15 R/W A2 A1 Pin Function 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC A0 BYTE DBEN DB07 DB06 DB05 DB04 DB03 DB02 DB01 NC DB00 VCC RESET TxA TxBE TxU TxE TxSQ TxC MM 28 29 PLCC 7 6 1 40 39
GND 9 DB08 10 DB09 11 DB10 12 DB11 13 DB12 14 DB13 15 DB14 16 DB15 17 R/W 18 A2 19 A1 20
SD00057
Figure 1. Pin Configuration 1995 May 01 2 853-1068 15179
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
ORDERING CODE
VCC = 5V +5% PACKAGES 40-Pin Ceramic Dual In-Line Package (DIP) 40-Pin Plastic Dual In-Line Package (DIP) 44-Pin Square Plastic Lead Chip Carrier (PLCC) Commercial 0C to +70C SCN2652AC2F40 / SCN68652AC2F40 SCN2652AC2N40 / SCN68652AC2N40 SCN2652AC2A44 / SCN68652AC2A44 Contact Factory Contact Factory Industrial -40C to +85C DWG # 0590B SOT129-1 SOT187-2
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG Storage temperature PARAMETER Operating ambient temperature2 RATING Note 4 -65 to +150 UNIT C C
VCC All inputs with respect to GND3 -0.3 to +7 V NOTES: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification is not implied. 2. For operating at elevated temperatures the device must be derated based on +150C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.
BLOCK DIAGRAM
16 BITS DATA BUS BUFFER 16 PARAMETER CONTROL SYNC/ADDRESS REGISTER PCSAR 8 BITS PARAMETER CONTROL REGISTER PCR
VCC GND
DB15- DB00
RESET MM INTERNAL BUS
RECEIVER DATA/STATUS REGISTER
RDSR
TRANSMITTER DATA/STATUS REGISTER
TDSR
A2-A0 BYTE R/W CE DBEN READ/ WRITE LOGIC AND CONTROL
16
16
RECEIVER LOGIC AND CONTROL
TRANSMITTER LOGIC AND CONTROL
S/F RxE RxA RxDA RxSA TxE TxA TxBE TxU
RxC RxSI
TxC TxSO
SD00058
Figure 2. Block Diagram
1995 May 01
3
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PIN DESCRIPTION
MNEMONIC DB15-DB00 A2-A0 BYTE CE R/W PIN NO. 17-10 24-31 19-21 22 1 18 TYPE I/O I I I I NAME AND FUNCTION Data Bus: DB07-DB00 contain bidirectional data while DB15-DB08 contain control and status information to or from the processor. Corresponding bits of the high and low order bytes can be wire OR'ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low. Address Bus: A2-A0 select internal registers. The four 16-bit registers can be addressed on a word or byte basis. See Register Address section. Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies 16-bit data bus transfers. Chip Enable: A high input permits a data bus operation when DBEN is activated. Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the addressed register. A low input causes the contents of the addressed register to be presented on the data bus. Data Bus Enable: After A2-A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read, the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is loaded into the addressed register and TxBE will be reset if TDSR was addressed. Reset: A high level initializes all internal registers (to zero) and timing. Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted. Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the receiver logic and initializes all receiver registers and timing. Receiver Active: RxA is asserted when the first data character of a message is ready for the processor. In the BOP mode this character is the address. The received address must match the secondary station address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR13) is set, the first non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA is reset by a low level at RxE. Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is ready to be presented to the processor. This output is reset when RDSRL is read. Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial data into the RxSR from RxSI. SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected. Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSRH except for RSOM. It is cleared when RDSRH is read. Receiver Serial Input: RxSI is the received serial data. Mark = `1', space = `0'. Transmitter Enable: A high level input enables the transmitter data path between TDSRL and TxSO. At the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG (BOP) or last character (BCP) is output on TxSO. Transmitter Active: TxA is asserted after TSOM (TDSR8) is set and TxE is raised. This output will reset when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO. Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control information or data. The processor should respond by loading theTDSR which resets TxBE. Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line fill depends on PCSAR11. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the falling edge of TxC. Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts data out of the TxSR to TxSO. Transmitter Serial Output: TxSO is the transmitted serial data. Mark = `1', space = `0'. +5V: Power supply. Ground: 0V reference ground.
DBEN RESET MM RxE
23 33 40 8
I I I I
RxA
5
O
RxDA* RxC S/F RxSA* RxSI TxE
6 2 4 7 3 37
O I O O I I
TxA TxBE*
34 35
O O
TxU*
36
O
TxC TxSO VCC GND
39 38 32 9
I O I I
*Indicates possible interrupt signal
1995 May 01
4
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 1.
Register Access
REGISTERS NO. OF BITS DESCRIPTION* PCSARH and PCR contain parameters common to the receiver and transmitter. PCSARL contains a programmable SYNC character (BCP) or secondary station address (BOP). RDSRH contains receiver status information. RDSRL = RxDB contains the received assembled character. TDSRH contains transmitter command and status information. TDSRL = TxDB contains the character to be transmitted
Addressable PCSAR PCR RDSR TDSR Parameter control sync/ address register Parameter control register Receive data/status register Transmit data/status register 16 8 16 16
Non-Addressable CCSR HSR RxSR TxSR RxCRC TxCRC Control character shift register Holding shift register Receiver shift register Transmitter shift register Receiver CRC accumulation register Transmitter CRC generation register 8 16 8 8 16 16 These registers are used for character assembly (CSSR (CSSR, HSR, RxSR), disassembly (TxSR), and CRC , ), y( ), accumulation/generation (RxCRC, TxCRC).
NOTES: *H = High byte - bits 15-8 L = Low byte - bits 7-0
Table 2.
FCS
Error Control
DESCRIPTION Frame check sequence is transmitted/received as 16 bits following the last data character of a BOP message. The divisor is usually CRC-CCITT (X16 + X12 + X5 + 1) with dividend preset to 1's but can be other wise determined by ECM. The inverted remainder is transmitter as the FCS. Block check character is transmitted/received as two successive characters following the last data character of a BCP message. The polynomial is CRC-16 (X16 + X15 + X2 + 1) or CRC-CCITT with dividend preset to 0's (as specified by ECM). The true remainder is transmitted as the BCC.
Table 3.
OPERATION BOP FLAG ABORT
Special Characters
BIT PATTERN 01111110 11111111 generation 01111111 detection FUNCTION Frame message Terminate communication Terminate loop mode repeater function Secondary station address
CHARACTER
GA Address BCP SYNC
01111111 (PCSARL)1 (PCSARL) or (TxDB)2 generation
BCC
Character synchronization
NOTES: 1. ( ) = contents of. 2. For IDLE = 0 or 1 respectively.
11 IDLE 10 9 ECM 9 RxCL 9 8 RxDB 8 8 7 6 5 4 3 21 0
15 PCSAR APA 15 PCR 15 RDSR RERR 15 TDSR TERR 14
14 PROTO 14 TxCL 14 13
13 SS/GA 13
12 SAM
S/AR
12 11 10 Tx Rx CL CL E E 11 ROR 10 RAB/ GA 10
12
ABC 13 12
REOM RSOM 9 8
11 TGA
NOT DEFINED
TABORT TEOM TSOM
TxDB
NOTE: Refer to Register Formats for mnemonics and description.
SD00059
Figure 3. Short Form Register Bit Formats
1995 May 01
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Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
BCP . CRC BOP . CRC BCP . CRC 8 RxSI M U X SEL FROM XMITTER SYNC FF 1-BIT DELAY SYNC/FLAG1 COMPARATOR CCSR (8) HSR (16) BOP . CRC ZERO (BOP) DELETION LOGIC ZERO DELETION CONTROL 8 M U X
TO RDSRL
RxSR (8)
MM BOP S/F BCP M U X
PARITY (BCP) LOGIC
RxCRC ACC
CRC-16 (BCP) OR CCRC-CCITT (BOP)
CRC-16 = 0 COMPARATOR CRC-CCIT = F0B8
RERR
RESET RxE RxA RxDA RxSA
RECEIVER CONTROL LOGIC
RxC NOTES: 1. Detected in SYNC FF and 7 MS bits of CCSR. 2. In BOP mode, a minimum of two data characters must be received to turn the receiver active.
SD00060
Figure 4. MPCC Receiver Data Path
FROM OR PCSAR (SYNC) L TDSARL
RESET TxE TxA TxBE TxU M U X BOP ZERO INSERTION LOGIC TRANSMITTER CONTROL LOGIC SYNC FF 1 BIT DELAY TxSO
TXSR (8)
TXCRC ACC (16) CRC-16 OR CRC-CCITT
ZERO INSERTION CONTROL
SEL1, 2 TxC CONTROL CHARACTER GENERATOR
BCP PARITY GENERATION
FLAG
ABORT
GA
NOTES: 1. TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR. 2. In BCP parity selected will be generated after each character is shifted out of TxSR.
SD00088
Figure 5. MPCC Transmitter Data Path
1995 May 01
6
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
FUNCTIONAL DESCRIPTION
The MPCC can be functionally partitioned into receiver logic, transmitter logic, registers that can be read or loaded by the processor, and data bus control circuitry. The register bit formats are shown in Figure 3 while the receiver and transmitter data paths are depicted in Figures 4 and 3.
should check RDSR9-15 each time RxSA is asserted. If RDSR9 is set, then RDSR12-15 should be examined. Receiver character length may be changed dynamically in response to RxDA: read the character in RxDB and write the new character length into RxCL. The character length will be changed on the next receiver character boundary. A received residual (short) character will be transferred into RxDB after the previous character in RxDB has been read, i.e. there will not be an overrun. In general the last two characters are protected from overrun. The CRC-CCITT, if specified by PCSAR8-10, is accumulated in RxCRC on each character following the FLAG. When the closing FLAG is detected in the CCSR, the received CRC is in the 16-bit HSR. At that time, the Receive End of Message bit (REOM) will be set; RxSA and RxDA will be asserted. The processor should read the last data character in RDSRL and the receiver status in RDSR9-15. If RDSR15 = 1, there has been a transmission error; the accumulated CRC-CCITT is incorrect. If RDSR12-14 0, last data character is not of prescribed length. Neither the received CRC nor closing FLAG are presented to the processor. The processor may drop RxE or leave it active at the end of the received message.
RECEIVER OPERATION General
After initializing the parameter control registers (PCSAR and PCR), the RxE input must be set high to enable the receiver data path. The serial data on the RxSI is synchronized and shifted into an 8-bit Control Character Shift Register (CCSR) on the rising edge of RxC. A comparison between CCSR contents and the FLAG (BOP) or SYNC (BCP) character is made until a match is found. At that time, the S/F output is asserted for one RxC time and the 16-bit Holding Shift Register (HSR) is enabled. The receiver then operates as described below.
BOP Operation
A flowchart of receiver operation in BOP mode appears in Figure 6. Zero deletion (after five ones are received) is implemented on the received serial data so that a data character will not be interpreted as a FLAG, ABORT, or GA. Bits following the FLAG are shifted through the CCSR, HSR, and into the Receiver Shift Register (RxSR). A character will be assembled in the RxSR and transferred to the RDSRL for presentation to the processor. At that time the RxDA output will be asserted and the processor must take the character no later than one RxC time after the next character is assembled in the RxSR. If not, an overrun (RDSR11 = 1) will occur and succeeding characters will be lost. The first character following the FLAG is the secondary station address. If the MPCC is a secondary station (PCSAR12 = 1), the contents of RxSR are compared with the address stored in PCSARL. A match indicates the forthcoming message is intended for the station; the RxA output is asserted, the character is loaded into RDSRL, RxDA is asserted and the Receive Start of Message bit (RSOM) is set. No match indicates that another station is being addressed and the receiver searches for the next FLAG. If the MPCC is a primary station, (PCSAR12 = 0), no secondary address check is made; RxA is asserted and RSOM is set once the first non-FLAG character has been loaded into RDSRL and RxDA has been asserted. Extended address field can be supported by software if PCSAR12 = 0. When the 8 bits following the address character have been loaded into RDSRL and RxDA has been asserted, RSOM will be cleared. The processor should read this 8-bit character and interpret it as the Control field. Received serial data that follows is read and interpreted as the information field by the processor. It will be assembled into character lengths as specified by PCR8-10. As before, RxDA is asserted each time a character has been transferred into RDSRL and is cleared when RDSRL is read by the processor. RDSRH should only be read when RxSA is asserted. This occurs on a zero to one transition of any bit in RDSRH except for RSOM. RxSA and all bits in RDSRH except RSOM are cleared when RDSRH is read. The processor
RxBCP Operation
The operation of the receiver in BCP mode is shown in Figure 7. The receiver initially searches for two successive SYNC characters, of length specified by PCR8-10, that match the contents of PCSARL. The next non-SYNC character or next SYNC character, if stripping is not specified (PCSAR13 = 0), causes RxA to be asserted and enables the receiver data path. Once enabled, all characters are assembled in RxSR and loaded into RDSRL. RxDA is active when a character is available in RDSRL. RxSA is active on a 0 to 1 transition of any bit in RDSRH. The signals are cleared when RDSRl or RDSRH are read respectively. If CRC-16 error control is specified by PCSAR8-10, the processor must determine the last character received prior to the CRC field. When that character is loaded into RDSRL and RxDA is asserted, the received CRC will be in CCSR and HSRL. To check for a transmission error, the processor must read the receiver status (RDSRH) and examine RDSR15. This bit will be set for one character time if an error free message has been received. If RDSR15 = 0, the CRC-16 is in error. The state of RDSR15 in BCP CRC mode does not set RxSA. Note that this bit should be examined only at the end of a message. The accumulated CRC will include all characters starting with the first non-SYNC character if PCSAR13 = 1, or the character after the opening two SYNCs if PCSAR13 = 0. This necessitates external CRC generation/checking when supporting IBM's BISYNC. This can be accomplished using the Philips Semiconductors SCN2653 Polynomial Generator/Checker. See Typical Applications. If VRC has been selected for error control, parity (odd or even) is regenerated on each character and checked when the parity bit is received. A discrepancy causes RDSR15 to be set and RxSA to be asserted. This must be sensed by the processor. The received parity bit is stripped before the character is presented to the processor. When the processor has read the last character of the message, it should drop RxE which disables the receiver logic and initializes all receiver registers and timing.
1995 May 01
7
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PROCESSOR
INITIALIZE PCSAR, PCR A
RxE = 1
RxE = 1? YES
NO
* TEST MADE EVERY RxC TIME FLAG IN CCSR* ? YES NO
S/F = 1 FOR ONE RxC BIT TIME
FLAG IN CCSR* ? NO
YES
ASSEMBLE CHARACTER IN RxSR. ZERO DELETION, ACCUMULATE CRC IF SPECIFIED
(1) OVERRUN (ROVRN) CAUSES LOSS OF SUBSEQUENT CHARACTERS
NO
IS IT 1st CHARACTER AFTER FLAG ? YES SEC. STATION MODE ? SECONDARY STATION ADDRESS IS CHARACTER = PCSARL ? YES NO
YES (PCSAR12 = 1)
START OF MESSAGE RxA = 1 RSOM = 1 FOR ONE CHARACTER TIME RxDA = 1 (PROCESSOR SHOULD READ RxDB)
NO (PCSAR12 = 0)
RxSR RxDB
RECEIVER STATUS BIT 0 1 EXCEPT RSOM ? YES
NO
RXSA = 1 (PROCESSOR SHOULD READ AND EXAMINE RDSRH - REOM, RAB/GA, ROVRN, ABC, RERR)
FLAG IN CCSR* ?
NO
RxE 0 ? NO YES A
S/F = 1 FOR ONE RxC BIT TIME REOM = 1, RxA = 0
YES - END OF MESSAGE
SD00061
Figure 6. BOP Receive
TRANSMITTER OPERATION General
After the parameter control registers (PCSAR and PCR) have been initialized, TxSO is held at mark until TSOM (TDSR8) is set and TxE is raised. Then, transmitter operation depends on protocol mode.
TxBOP Operation
Transmitter operation for BOP is shown in Figure 8. A FLAG is sent after the processor sets the Transmit Start of Message bit (TSOM) and raises TxE. The FLAG is used to synchronize the message that follows. TxA will also be asserted. When TxBE is asserted by the
1995 May 01
8
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
MPCC, the processor should load TDSRL with the first character of the message. TSOM should be cleared at the same time TDSRL is loaded (16-bit data bus) or immediately thereafter (8-bit data bus). FLAGS are sent as long as TSOM = 1. For counting the number of FLAGs, the processor should reassert TSOM in response to the assertion of TxBE.All succeeding characters are loaded into TDSRL by the processor when TxBE = 1. Each character is serialized in TxSR and transmitted on TxSO. Internal zero insertion logic stuffs a "0" into the serial bit stream after five successive "1s" are sent. This insures a data character will not match a FLAG, ABORT, or GA reserved control character. As each character is transmitted, the Frame Check Sequence (FCS) is generated as specified by Error Control Mode (PCSAR8-10). The FCS should be the CRC-CCITT polynomial (X16 + X12 + X5 + 1) preset to 1s. If an underrun occurs (processor is not keeping up with the transmitter), TxU and TERR (TDSR15) will be asserted with ABORT or FLAG used as the TxSO line fill depending on the state of IDLE (PCSAR11). The processor must set TSOM to reset the underrun condition. To retransmit the message, the processor should proceed with the normal start of message sequence. A residual character of 1 to 7 bits may be transmitted at the end of the information field. In response to TxBE, write the residual character length into TxCL and load TxDB with the residual character. Dynamic alteration of character length should be done in exactly the same sequence. The character length will be changed on the next transmit character boundary. After the last data character has been loaded into TDSRL and sent to TxSR (TxBE = 1), the processor should set TEOM (TDSR9). The MPCC will finish transmitting the last character followed by the FCS and the closing FLAG. The processor should clear TEOM and drop TxE when the next TxBE is asserted. This corresponds to the start of closing FLAG transmission. When TxE has been dropped. TxA will be low 1 1/2 bit times after the last bit of the closing FLAG has been transmitted. TxSO will be marked after the closing FLAG has been transmitted. If TxE and TEOM are high, the transmitter continues to send FLAGs. The processor may initiate the next message by resetting TEOM and setting TSOM, or by loading TDSRL with a data character and then simply resetting TSOM (without setting TSOM).
CRC-16, if specified by PCSAR8-10, is generated on each character transmitted from TDSRL when TSOM =0. The processor must set TEOM = 1 after the last data character has been sent to TxSR (TxBE = 1). The MPCC will finish transmitting the last data character and the CRC-16 field before sending SYNC characters which are transmitted as long as TEOM = 1. If SYNCs are not desired after CRC-16 transmission, the processor should clear TEOM and lower TxE when the TxBE corresponding to the start of CRC-16 transmission is asserted. When TEOM = 0, the line is marked and a new message may be initiated by setting TSOM and raising TxE. If VRC is specified, it is generated on each data character and the data character length must not exceed 7 bits. For software LRC or CRC, TEOM should be set only if SYNC's are required at the end of the message block. SPECIAL CASE: The capability to transmit 16 spaces is provided for line turnaround in half duplex mode or for a control recovery situation. This is achieved by setting TSOM and TEOM, clearing TEOM when TxBE = 1, and proceeding as required.
PROGRAMMING
Prior to initiating data transmission or reception, PCSAR and PCR must be loaded with control information from the processor. The contents of these registers (see Register Format section) will configure the MPCC for the user's specific data communication environment. These registers should be loaded during power-on initialization and after a reset operation. They can be changed at any time that the respective transmitter or receiver is disabled. The default value for all registers is zero. This corresponds to BOP, primary station mode, 8-bit character length, FCS = CRC-CCITT preset to 1s. For BOP mode the character length register (PCR) may be set to the desired values during system initialization. The address and control fields will automatically be 8-bits. If a residual character is to be transmitted, TxCL should be changed to the residual character length prior to transmission of that character.
DATA BUS CONTROL
The processor must set up the MPCC register address (A2-A0), chip enable (CE), byte select (BYTE), and read/write (R/W) inputs before each data bus transfer operation. During a read operation (R/W = 0), the leading edge of DBEN will initiate an MPCC read cycle. The addressed register will place its contents on the data bus. If BYTE = 1, the 8-bit byte is placed on DB15-08 or DB07-00 depending on the H/L status of the register addressed. Unused bits in RDSRL are zero. If BYTE = 0, all 16 bits (DB15-00) contain MPCC information. The trailing edge of DBEN will reset RxDA and/or RxSA if RDSRL or RDSRH is addressed respectively. DBEN acts as the enable and strobe so that the MPCC will not begin its internal read cycle until DBEN is asserted. During a write operation (R/W = 1), data must be stable on DB15-08 and/or DB07-00 prior to the leading edge of DBEN. The stable data is strobed into the addressed register by DBEN. TxBE will be cleared if the addressed register was TDSRH or TDSRL.
TxBCP Operation
Transmitter operation for BCP mode is shown in Figure 9. TxA will be asserted after TSOM = 1 and TxE is raised. At that time SYNC characters are sent from PCSARL or TDSRL (IDLE = 0 or 1) as long as TSOM = 1. TxBE is asserted at the start of transmission of the first SYNC character. For counting the number of SYNCs, the processor should reassert TSOM in response to the assertion of TxBE. When TSOM = 0 transmission is from TDSRL, which must be loaded with characters from the processor each time TxBE is asserted. If this loading is delayed for more than one character time, an underrun results: TxU and TERR are asserted and the TxSO line fill depend on IDLE (PCSAR11). The processor must set TSOM and retransmit the message to recover. This is not compatible with IBM's BISYNC, so that the user must not underrun when supporting that protocol.
1995 May 01
9
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PROCESSOR
INITIALIZE PCSAR, PCR A
RxE = 1
RxE = 1?
NO
YES SYNC DETECT1 IN CCSR? YES SYNC DETECT2 IN CCSR? YES SYNC DETECT IN CCSR? NO RxA = 1 ASSEMBLE CHARACTER IN RxSR, STRIP VRC IF SPECIFIED, ACCUMULATE CRC IF SPECIFIED RxDA = 1 (PROCESSOR SHOULD READ RxDB) (1) SYNCs ARE ASSEMBLED (2) OVERRUN (ROVRN) CAUSES LOSS OF SUBSEQUENT CHARACTERS STRIP SYNC (PCSAR13) = 1? NO
NO
S/F = 1 FOR ONE RxC BIT TIME
NO
YES
YES
RxSR RxDB
ANY RECEIVER STATUS BIT 01 ? RxSA = 1 (PROCESSOR SHOULD READ AND EXAMINE RDSRH - ROVRN, RERR (IF VRC SPECIFIED) RxE = 0 WHEN LAST CHARACTER HAS BEEN SERVICED YES
NO
RxE = 0? YES A
NO
NOTES: 1. Test made every RxC time. 2. Test made on Rx character boundary.
SD00062
Figure 7. BCP Receive
1995 May 01
10
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
INITIALIZE PCSAR, PCR, TDSRH A
(PROCESSOR MUST CLEAR TABORT/GA IN RESPONSE TO TxBE = 1)
TxSO = MARK
TSOM = 1 TxE = 1 B TxA = 1 TxBE = 1 PROCESSOR SHOULD LOAD TxDB AND TSOM = 0)
TSOM TxE = 1? YES
NO
TRANSMIT FLAG ON TxSO
TSOM = 0? (PROCESSOR MAY SET TABORT, TGA, AS REQUIRED) YES
NO
TABORT = 1? NO
YES
TxSO = ABORT = 11111111 IF IDLE = 0 FLAG = 01111110 IF IDLE = 1
ON UNDERRUN: TxU = 1, TERR = 1 (PROCESSOR SHOULD SET TSOM)
UNDER RUN? NO
YES
TxSO = ABORT IF IDLE = 0 FLAG IF IDLE = 1
TxBE = 1 (PROCESSOR SHOULD LOAD TxDB WITH NEXT DATA CHAR)
SERIALIZE DATA CHARACTER IN TxDB, ZERO INSERTION, ACCUMULATE CRC IF SPECIFIED BY ECM, TRANSMIT ON TxSO
NO
TSOM = 1? YES B
TEOM = 1? YES TRANSMIT ACCUMULATED FCS (IF SPECIFIED) AS INVERTED REMAINDER
NO
TxBE = 1
TRANSMIT FLAG ON TxSO*
(PROCESSOR SHOULD RESET TEOM AND SET TSOM OR DROP TxE)
TEOM = 0? YES TSOM = 1?
NO
B YES
NO TxE = 0? YES A
NO TxA = 0
*GA will be transmitted if TGA is set together with TEOM.
Figure 8. BOP Transmit
SD00063
1995 May 01
11
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PROCESSOR
INITIALIZE PCSAR, PCR, TDSRH A TxSO = MARK
TSOM = 1 TxE = 1 TxA = 1
TSOM, TxE = 1? YES
NO B
TxBE = 1
TRANSMIT SYNC ON TxSO SYNC FROM PCSARL - IDLE = 0 SYNC FROM TxDB IDLE = 1
AFTER SYNC(S), PROCESSOR LOADS DATA CHARACTER IN TxDB AND TSOM = 0
TSOM = 0? YES
NO
TxBE = 1 (PROCESSOR SHOULD LOAD TxDB)
SERIALIZE DATA CHARACTER IN TxDB, GENERATE VRC OR ACCUMULATE CRC AS SPECIFIED, TRANSMIT ON TxSO
(PROCESSOR SHOULD GET TEOM AT END OF MESSAGE IF CRC SPECIFIED)
TEOM = 1?
NO
NO C
UNDERRUN? YES
YES TxU = 1, TERR = 1 (PROCESSOR SHOULD SET TSOM = 1)
TRANSMIT ACCUMULATED CRC SPECIFIED (IF NO CRC, TEOM SHOULD = 0)
TxSO = SYNC FROM PCSARL IF IDLE = 0 MARK IF IDLE = 1 UNTIL TSOM = 1
B TxBE = 1 (PROCESSOR SHOULD CLEAR TEOM AND DROP TxE) C
TEOM = 0? YES
NO
TxSO = SYNC OR TxDB DEPENDING ON IDLE BIT
TxE = 0? TxA = 0 A YES
NO
SD00064
Figure 9. BCP Transmit
1995 May 01
12
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 4.
Byte = 0
MPCC Register Addressing
A2 0 0 1 1 A1 0 1 0 1 0 0 1 1 0 0 1 1 A0 X X X X 0 1 0 1 0 1 0 1 REGISTER RDSR TDSR PCSAR PCR* RDSRL RDSRH TDSRL TDSRH PCSARL PCSARH PCRL* PCRH (16-Bit Data Bus = DB15 - DB00)
Byte = 1
(8-Bit Data Bus = DB7-0 or DB15-8**) 0 0 0 0 1 1 1 1
NOTES: * PCR lower byte does not exist. It will be all "0"s when read. ** Corresponding high and low order pins must be tied together.
Table 5.
BIT 00-07 08-10
Parameter Control Register (PCR)-(R/W)
NAME Not Defined RxCL BOP/BCP Receiver character length is loaded by the processor when RxCLE = 0. The character length is valid after transmission of single byte address and control fields have been received. 10 0 0 0 0 1 1 1 1 9 0 0 1 1 0 0 1 1 8 0 1 0 1 0 1 0 1 Char length (bits) 8 1 2 3 4 5 6 7 MODE FUNCTION
11 12 13-15
RxCLE TxCLE TxCL
BOP/BCP BOP/BCP BOP/BCP
Receiver character length enable should be zero when the processor loads RxCL. The remaining bits of PCR are not affected during loading. Always 0 when read. Transmitter character length enable should be zero when the processor loads TxCL. The remaining bits of PCR are not affected during loading. Always 0 when read. Transmitter character length is loaded by the processor when TxCLe = 0. Character bit length specification format is identical to RxCL. It is valid after transmission of single byte address and control fields.
1995 May 01
13
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 6.
BIT 00-07
Parameter Control SYNC/Address Register (PCSAR)-(R/W)
NAME S/AR MODE BOP FUNCTION SYNC/address register. Contains the secondary station address if the MPCC is a secondary station. The contents of this register is compared with the first received non-FLAG character to determine if the message is meant for this station. SYNC character is loaded into this register by the processor. It is used for receive and transmit bit synchronization with bit length specified by RxCL and TxCL. Error Control Mode 10 9 8 Suggested Mode Char. length CRC-CCITT preset to 1's 0 0 0 BOP 1-8 CRC-CCITT preset to 0's 0 0 1 BCP 8 Not used 0 1 0 --- CRC-16 preset to 0's 0 1 1 BCP 8 VRC odd 1 0 0 BCP 5-7 VRC even 1 0 1 BCP 5-7 Not used 1 1 0 --- No error control 1 1 1 BCP/BOP 5-8 ECM should be loaded by the processor during initialization or when both data paths are idle. Determines line fill character to be used if transmitter underrun occurs (TxU asserted and TERR set) and transmission of special characters for BOP/BCP. IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1. IDLE = 1, transmit FLAG characters during underrun and when TABORT = 1. IDLE = 0 transmit initial SYNC characters and underrun line fill characters from theS/AR. IDLE = 1 transmit initial SYNC characters from TxDB and marks TxSO during underrun. Secondary Address Mode = 1 if the MPCC is a secondary station. This facilitates automatic recognition of the received secondary station address. When transmitting, the processor must load the secondary address into TxDB. SAM = 0 inhibits the received secondary address comparison which serves to activate the receiver after the first non-FLAG character has been received. Strip SYNC/Go Ahead. Operation depends on mode. SS/GA = 1 is used for loop mode only and enables GA detection. When a GA is detected as a closing character, REOM and RAB/GA will be set and the processor should terminate the repeater function. SS/GA = 0 is the normal mode which enables ABORT detection. It causes the receiver to terminate the frame upon detection of an ABORT or FLAG. SS/GA = 1, causes the receiver to strip SYNC's immediately following the first two SYNC's detected. SYNC's in the middle of a message will not be stripped. SS/GA = 0, presents any SYNC's after the initial two SYNC's to the processor. Determines MPCC Protocol mode PROTO = 0 PROTO = 1 All parties address. If this bit is set, the receiver data path is enabled by an address field of `11111111' as well as the normal secondary station address.
BCP 08-10 ECM BOP/BCP
11
IDLE BOP BCP
12
SAM
BOP
13
SS/GA BOP
BCP
14
PROTO BOP BCP
15
APA
BOP
1995 May 01
14
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 7.
BIT 00-07 08
Transmit Data/Status Register (TDSR) (R/W except TDSR15)
NAME TxDB TSOM BOP MODE BOP/BCP FUNCTION Transmit data buffer. Contains processor loaded characters to be serialized in TxSR and transmitted on TxSO. Transmitter start of message. Set by the processor to initiate message transmission provided TxE = 1. TSOM = 1 generates FLAGs. When TSOM = 0 transmission is from TxDB and FCS generation (if specified) begins. FCS, as specified by PCSAR8-10, should be CRC-CCITT preset to 1's. TSOM = 1 generates SYNCs from PCSARL or transmits from TxDB for IDLE = 0 or 1 respectively. When TSOM = 0 transmission is from TxDB and CRC generation (if specified) begins. Transmit end of message. Used to terminate a transmitted message. TEOM = 1 causes the FCS and the closing FLAG to be transmitted following the transmission of the data character in TxSR. FLAGs are transmitted until TEOM = 0. ABORT or GA are transmitted if TABORT or TGA are set when TEOM = 1. TEOM = 1 causes CRC-16 to be transmitted (if selected) followed by SYNCs from PCSARL or TxDB (IDLE = 0 or 1). Clearing TEOM prior to the end of CRC-16 transmission (when TxBE = 1) causes TxSO to be marked following the CRC-16. TxE must be dropped before a new message can be initiated. If CRC is not selected, TEOM should not be set. Transmitter abort = 1 will cause ABORT or FLAG to be sent (IDLE = 1 or 1) after the current character is transmitted. (ABORT = 11111111) Transmit go ahead (GA) instead of FLAG when TEOM = 1. This facilitates repeater termination in loop mode. (GA = 01111111) Transmitter error = 1 indicates the TxDB has not been loaded in time (one character time-1/2 TxC period after TxBE is asserted) to maintain continuous transmission. TxU will be asserted to inform the processor of this condition. TERR is cleared by setting TSOM. See timing diagram. ABORT's or FLAG's are sent as fill characters (IDLE = 0 or 1) SYNC's or MARK's are sent as fill characters (IDLE = 0 or 1). For IDLE = 1 the last character before underrun is not valid.
BCP
09
TEOM BOP
BCP
10 11 12-14 15
TABORT TGA Not Defined TERR
BOP BOP
Read only
BOP BCP
1995 May 01
15
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 8.
BIT 00-07 08
Receiver Data/Status Register (RDSR)-(Read Only)
NAME RxDB RSOM MODE BOP/BCP BOP FUNCTION Receiver data buffer. Contains assembled characters from the RxSR. If VRC is specified, the parity bit is stripped. Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and the latter character matches the secondary station if SAM = 1. RxA will be asserted when RSOM = 1. RSOM resets itself after one character time and has no affect on RxSA. Receiver end of message = 1 when the closing FLAG is detected and the last data character is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on reading RDSRH, reset operation, or dropping of RxE. Received ABORT or GA character = 1 when the receiver senses an ABORT character if SS/GA = 0 or a GA character if SS/GA = 1. RAB/GA is cleared on reading RDSRH, reset operation, or dropping of RxE. A received abort does not set RxDA. Receiver overrun = 1 indicates the processor has not read last character in the RxDB within one character time + 1/2 RxC period after RxDA is asserted. Subsequent characters will be lost. ROR is cleared on reading RDSRH, reset operation, or dropping of RxE. Assembled bit count. Specifies the number of bits in the last received data character of a message and should be examined by the processor when REOM = 1(RxDA and RxSA asserted). ABC = 0 indicates the message was terminated (by a flag or GA) on a character boundary as specified by PCR8-10. Otherwise, ABC = number of bits in the last data character. ABC is cleared when RDSRH is read, reset operation, or dropping RxE. The residual character is right justified inRDSRL. Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or when the processor determines the last data character of the message in BCP with CRC or when RxSA is set in BCP with VRC. CRC-CCITT preset to 1's/0's as specified by PCSAR8-10: RERR = 1 indicates FCS error (CRC F0B8 or 0) RERR = 0 indicates FCS received correctly (CRC = F0B8 or = 0) CRC-16 preset to 0's on 8-bit characters specified by PSCAR8-10: RERR = 1 indicates CRC-16 received correctly (CRC = 0). RERR = 0 indicates CRC-16 error (CRC0) VRC specified by PCSAR8-10: RERR = 1 indicates VRC error RERR = 0 indicates VRC is correct.
09
REOM
BOP
10
RAB/GA
BOP
11
ROR
BOP/BCP
12-14
ABC
BOP
15
RERR
BOP/BCP
DC ELECTRICAL CHARACTERISTICS1, 2
PARAMETER Input voltage VIL Low VIH High Output voltage VOL Low VOH High ICC Power supply current Leakage current IIL Input IOL Output Capacitance CIN Input COUT Output IOL = 1.6mA IOH = -100A VCC = 5.25V, TA = 0C VIN = 0 to 5.25V VOUT = 0 to 5.25V VIN = 0V, f = 1MHz VOUT = 0V, f = 1MHz TEST CONDITIONS LIMITS Min Typ Max 0.8 2.0 0.4 2.4 150 10 10 20 20 mA A V UNIT
V
pF
1995 May 01
16
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
AC ELECTRICAL CHARACTERISTICS1, 2, 3
PARAMETER Set-up and hold time tACS Address/control set-up tACH Address/control hold tDS Data bus set-up (write) tDH Data bus hold (write) tRXS Receiver serial data set-up tRxH Receiver serial data hold Pulse width tRES RESET tDBEN DBEN Delay Time tDD Data bus (read) tTxD Transmit serial data tDBEND DBEN to DBEN delay tDF f tCLK1 tCLK2 tCLK0 Data bus float time (read) Clock (RxC, TxC) frequency Clock high (MM = 0) Clock high (MM = 1) Clock low 165 240 240 2MHz CLOCK Min 50 0 50 0 150 150 250 250 Typ Max UNIT
ns
ns m4 170 250
ns
200 150 2.0 ns MHz ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 2. All voltage measurements are referenced to ground. All time measurements are at 0.8V or 2.0V. Input voltage levels for testing are 0.4V and 2.4V. 3. Output load CL = 100pF. 4. m = TxC low and applies to writing to TDSRH only.
TIMING DIAGRAMS
RESET
DBEN
RESET AND WRITE DATA BUS
tDBEN
A0, A2 tACS RESET tRES D0-D15 (READ) D0-D15 (WRITE) tDS tDH CE, R/W, BYTE tACS FLOATING NOT VALID tDD VALID tACH FLOATING tDF tACH
SD00065
Figure 10. Timing Diagrams
1995 May 01
17
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
CLOCK
1/f
TxC
tCLK1
tCLK0
TxSO TxD
RxC tCLK0 tRxS tCLK1 tRxH
RxSI
SD00066
Figure 11. Timing Diagrams (cont.) TRANSMIT - START OF MESSAGE
TxC 8 TxC1 TxSO MARK SYNC/FLAG1 1ST CHAR
3 TxBE
SET TSOM
LOAD 1st CHAR
RESET TSOM
LOAD 2nd CHAR
DBEN
TxE
2 TxA
NOTES: 1. SYNC may be 5 to 8 bits and will contain parity bit as specified. 2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised. 3. TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes low relative to DBEN falling edge when writing into TDSRH and/or TDSRL. It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing-End of Message).
SD00067
Figure 12. Timing Diagrams (cont.) 1995 May 01 18
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT - END OF BOP MESSAGE
TxC
TxSO
NEXT TO LAST CHAR
LAST CHAR
CRC
FLAG
MARK
TxBE1 LOAD LAST CHAR SET TEOM RESET TEOM
DBEN
TxE2
TxA3 NOTES: 1. TxBE goes low relative to the falling edge of DBEN corresponding to loading TDSRH/L. It goes high one TxC before character transmission begins and also when TxA has been dropped. 2. TxE can be dropped before resetting TEOM if TxBE (corresponding to the closing FLAG) is high. Alternatively TxE can remain high and a new message initiated. 3. TxA goes low after TxE has been dropped and 1 1/2 TxC's after the last bit of the closing FLAG has been transmitted. SD00068
Figure 13. Timing Diagrams (cont.)
TRANSMIT TIMING - END OF BCP MESSAGE
TxC
TxSO
NEXT TO LAST CHAR
LAST CHAR
CRC1
MARK
TxBE
LOAD LAST CHAR
SET TEOM
RESET TEOM
DBEN
TxE
TxA
NOTE: 1. When SCN2652 generated CRC is not required. TEOM should only be set if SYNCs are to follow the message block. In that case, TxE should be dropped in response to TxBE (which corresponds to the start of transmission of the last character). When CRC is required, TxE must be dropped before CRC transmission is complete. Otherwise, the contents of TxDB will be shifted out on TxSO. This facilitates transmission of contiguous messages.
SD00069
Figure 14. Timing Diagrams (cont.)
1995 May 01
19
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT UNDERRUN
TxC
TxU1 SET TSOM DBEN2 NOTES: 1. TxU goes active relative to TxC falling edge if TxBE has not been serviced after n-1/2 TxC times (where n = transmit character length). TxU is reset on the TxC falling edge following assertion of the TSOM command. 2. An underrun will occur at the next character boundary if TEOM is reset and the transmitter remains enabled, unless the TSOM command is asserted or a character is loaded into the TxDB.
SD00070
Figure 15. Timing Diagrams (cont.)
RECEIVE - START OF MESSAGE
RxC
1 RxA
RxDA2
1st CHAR READY TO BE READ
2nd CHAR READY TO BE READ
1st CHAR READ DBEN
2nd CHAR READ
S/F3
RxE
NOTES: 1. RxA goes high relative to falling edge of RxC when RxE is high and: a. A data character following two SYNC's is in RxDB (BCP mode). b. Character following FLAG is in RxDB (BOP primary station mode). c. Character following FLAG is in RxDB and character matches the secondary station address or all parties address (BOP secondary station mode). 2. RxDA goes high on RxC falling edge when a character in RxDB is ready to be read. It comes up before RxSA and goes low on the falling edge of DBEN when RxDB is read. 3. S/F goes high relative to rising edge of RxC anytime a SYNC (BCP) or FLAG (BOP) is detected.
SD00071
Figure 16. Timing Diagrams (cont.)
1995 May 01
20
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
RECEIVE END OF MESSAGE
RxC
RxDA
RxSA1 READ DATA DBEN (8-BIT) S/F READ STATUS
RxE2
RxA3 NOTES: 1. At the end of a BOP message, RxSA goes high when FLAG detection (S/F 1) forces REOm to be set. Processor should read the last data character (RDSRL) and status (RDSRH) which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status. 2. RxE must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation). 3. RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active.) or when RxE is dropped. SD00072
Figure 17. Timing Diagrams (cont.)
TYPICAL APPLICATIONS
SCN2652 MPCC MICROPROCESSOR INTERFACE
RESET TS BUFFER RESET DATA BUS DB0-DB7 8-BIT P CLOCK ADDRESS CONTROL "1" BYTE A2-A0, R/W DBEN CE MPCC SCN2652 TxSO LD RxC LR SYNCHRONOUS MODEM TxC
STATUS
LR
RxSI
LR
RxE MODEM CONTROL LOGIC
TxE
RTS, CTS, DTR, DSR, DCD
DCD
CTS
NOTES: 1. Possible P interrupt requests are: RxDA RxSA TxBE TxU 2. Other SCN2652 status signals and possible uses are S F line idle indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, line turn around control. 3. Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice-versa. 4. RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low. 5. Corresponding high and low order bits of DB must be OR tied.
SD00073
Figure 18. Typical Applications
1995 May 01
21
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TYPICAL APPLICATIONS (Continued)
DMA/PROCESSOR INTERFACE
DATA BUS 8 OR 16 BITS
WORD COUNT ADDRESS PTR R/W CONTROL
RDREQ
DB15-DB00 RxDA RxA RxE RxSA TxA TxE
DB15-DB00
DATA BUS
TO PROCESSOR WRREQ TxBE
DMA CONTROLLER SCN2652 ADDRESS AND CONTROL
SCN2652
TxU S/F
A2-A0 BYTE R/W CE DBEN
RESET MM
PROCESSOR (P) AND SUPPORT LOGIC: 1. INITIALIZES SCN2652 2. SETS/RESETS TSOM, TEOM 3. RESPONDS TO RxSA
RxDA TxBE R/W MEMORY
ADDRESS R/W CONTROLS
RxC TxC RxSI TxSO
ADDRESS, R/W, CONTROL
ADDRESS, CE, R/W
MODEM OR DCE
SYSTEM ADDRESS AND CONTROL BUS
For non-DMA operation TxBE and RxDA are set to the processor which then loads or reads data characters as required.
SD00074
Figure 19. Typical Applications (cont.)
CHANNEL INTERFACE
BAUD RATE GENERATOR LD LR
BAUD RATE GENERATOR
TxC
RxC LR LD
TxC
RxC
COMPUTER OR TERMINAL
MPCC SCN2652
MPCC SCN2652
COMPUTER OR TERMINAL
TxSO
LD
LR
RxSI
RxSI
LR
LD
TxSO
No Modem - DC Baseband Transmission
SD00075
Figure 20. Typical Applications (cont.)
1995 May 01
22
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
SCN2652/SCN2653 INTERFACE TYPICAL PROTOCOLS: BISYNC, DDCMP, SDLC, HDLC
INTERRUPTS
TxBE, TxU, RxDA, RxSA
DB7-DB0
MPCC SCN2652 A2 A1 A0 R/W DBEN CE
TxD RxD
TxC RxC DB7-DB0
CPU CE0 PGC SCN2653 A1 R/W A0 CE1
INT (OPEN DRAIN) 5V
SD00076
Figure 21. Typical Applications (cont.)
1995 May 01
23
1998 May 01 24
0590B
Philips Semiconductors
Multi-protocol communications controller (MPCC)
853-0590B 06688 0.098 (2.49) 0.040 (1.02) SEE NOTE 6 0.098 (2.49) 0.040 (1.02)
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
NOTES: 1. Controlling dimension: Inches. Millimeters are shown in parentheses. 2. Dimension and tolerancing per ANSI Y14. 5M-1982. 3. "T", "D", and "E" are reference datums on the body and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. 4. These dimensions measured with the leads constrained to be perpendicular to plane T. 5. Pin numbers start with Pin #1 and continue counterclockwise to Pin #40 when viewed from the top. 6. Denotes window location for EPROM products.
-E-
0.598 (15.19) 0.571 (14.50)
PIN # 1 -D-
0.100 (2.54) BSC 2.087 (53.01) 2.038 (51.77) 0.620 (15.75) 0.590 (14.99) (NOTE 4) 0.175 (4.45) 0.145 (3.68)
0.070 (1.78) 0.050 (1.27) 0.225 (5.72) MAX.
-T- SEATING PLANE
0.165 (4.19) 0.125 (3.18)
0.055 (1.40) 0.020 (0.51)
BSC 0.600 (15.24) (NOTE 4) 0.695 (17.65) 0.600 (15.24)
0.023 (0.58) 0.015 (0.38)
T
ED
0.010 (0.254) 0.015 (0.38) 0.010 (0.25)
SCN2652/SCN68562
Product specification
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1998 May 01
25
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1998 May 01
26
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
NOTES
1998 May 01
27
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98
Philips Semiconductors
1998 May 01 28

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